Whenever the PCI Express controller is in root complex mode and it receives an inbound INTx asserted or negated messages transaction, it asserts or negates an equivalent internal INTx signal to the PIC. This INTx virtual-wire interrupt signaling machanism replaces the PCI standard sideband interrupts(INTA, INTB, INTC and INTD) that historically were connected to the IRQn external interrupts input. The internal INTx signals from the PCI Express controller are logically combined with the interrupt request (IRQn) signals so that they share the same OpenPIC external interrupt controlled by the associated EIVPRn and EIDRn registers.

EIVPR11 External interrup11(IRQ11) vector/priority register or PCIe3-INTD vector/priority register.

PCI Express 3
____________________
|    INTA    IRQ8    |    
|    INTB    IRQ9    |
|    INTC    IRQ10    |
|    INTD    IRQ11    |
|___________________|

PCIe INTx/IRQn sharing